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data sheet ICS844011ag revision a august 27, 2012 1 ?2012 integrated device technology, inc. femtoclock ? crystal-to-lvds clock generator ICS844011 general description the ICS844011 is a fibre channel clock generator. the ICS844011 uses an 18pf parallel resonant crystal. for fibre channel applications, a 26.5625mhz crystal is used. the ICS844011 has excellent <1ps phase jitter performance, over the 637khz - 10mhz integration range. the ICS844011 is packaged in a small 8-pin tssop, making it ideal for use in system s with limited board space. features one differential lvds clock output pair crystal interface designed for 18pf parallel resonant crystals vco range: 490mhz ? 680mhz rms phase jitter @ 106.25mhz, using a 26.5625mhz crystal (637khz - 10mhz): 0.97ps (typical) rms phase jitter @ 100mhz, (637khz - 10mhz): 0.77ps (typical) full 3.3v or 2.5v operating supply available in lead-free (rohs 6) package 0c to 70c ambient operating temperature common configuration table ? fibre channel inputs output frequency (mhz) crystal frequency (mhz) m n mu ltiplication value m/n 26.5625 24 6 4 106.25 25 24 6 4 100 osc phase detector vco 490mhz - 680mhz m = 24 (fixed) n = 6 (fixed) qnq oe xtal_in xtal_out pullup 12 3 4 87 6 5 v dda gnd xtal_out xtal_in v dd qnq oe block diagram pin assignment ICS844011 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view
ICS844011ag revision a august 27, 2012 2 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator pin description and ch aracteristic tables table 1. pin descriptions note: pullup refers to an internal input resistor. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. oe control function table number name type description 1v dda power analog power supply. 2g n dp o w e r power supply ground. 3, 4 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 5 oe input pullup output enable pin. lvcmos/lvttl interface levels. 6, 7 nq, q output differential clock output. lvds interface levels. 8v dd power core supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4p f r pullup input pullup resistor 51 k ? input output enable oe 0 output q, nq pair is dis abled in high-impedance state. 1 (default) output q, nq is enabled.
ICS844011ag revision a august 27, 2012 3 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v5%, t a = 0c to 70c table 4b. power supply dc characteristics, v dd = 2.5v5%, t a = 0c to 70c table 4c. lvcmos/lvttl input dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i xtal_in other input 0v to v dd -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma15ma package thermal impedance, ja 129.5c/w (0 mps) storage temperature, t stg -65c to 150c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.12 3.3 v dd v i dd power supply current 108 ma i dda analog supply current 12 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.12 2.5 v dd v i dd power supply current 102 ma i dda analog supply current 12 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current oe v dd = v in = 3.465v or 2.625v 5 a i il input low current oe v dd = 3.465v or 2.625v, v in = 0v -150 a
ICS844011ag revision a august 27, 2012 4 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator table 4d. lvds dc characteristics, v dd = 3.3v5%, t a = 0c to 70c table 4e. lvds dc characteristics, v dd = 2.5v5%, t a = 0c to 70c table 5. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 250 350 450 mv ? v od v od magnitude change 50 mv v os offset voltage 1.1 1.3 1.5 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 250 350 450 mv ? v od v od magnitude change 50 mv v os offset voltage 0.9 1.2 1.5 v ? v os v os magnitude change 50 mv parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 26.5625 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7p f
ICS844011ag revision a august 27, 2012 5 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator ac characteristics table 6a. ac characteristics, v dd = 3.3v5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: please refer to the phase noise plot. table 6b. ac characteristics, v dd = 2.5v5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f out output frequency 100 106.25 mhz t jit(?) rms phase jitter (random); note 1 106.25mhz, integration range: 637khz ? 10mhz 0.97 ps 100mhz, integration range: 637khz ? 10mhz 0.77 ps t r / t f output rise/fall time 20% to 80% 150 400 ps odc output duty cycle 48 52 % symbol parameter test conditions minimum typical maximum units f out output frequency 100 106.25 mhz t jit(?) rms phase jitter (random) 106.25mhz, integration range: 637khz ? 10mhz 1.26 ps 100mhz, integration range: 637khz ? 10mhz 0.98 ps t r / t f output rise/fall time 20% to 80% 150 400 ps odc output duty cycle 48 52 %
ICS844011ag revision a august 27, 2012 6 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator typical phase noise at 106.25mhz (3.3v) noise power dbc hz offset frequency (hz)
ICS844011ag revision a august 27, 2012 7 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator parameter measurement information 3.3v lvds output load test circuit output duty cycle/pulse width/period differential output voltage setup output rise/fall time 2.5v lvds output load test circuit rms phase jitter offset voltage setup scope qx nqx 3.3v5% power supply +? float gnd v dd v dda t pw t period t pw t period odc = x 100% nq q 100 out out dc input v od / ? v od v dd 20% 80% 80% 20% t r t f v od nq q scope qx nqx 2.5v5% power supply +? float gnd v dd v dda offset frequency f 1 f 2 phase noise plot area under curve defined by the offset frequency markers rms phase jitter = noise power 2 * * ? 1 * out out lvds dc input ? v os / ? v os v dd
ICS844011ag revision a august 27, 2012 8 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator applications information overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driv er (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl terminatio n with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be pl aced in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a quartz crystal as the input. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpecl driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r150 r250 r350
ICS844011ag revision a august 27, 2012 9 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 2a can be used with either type of output structure. figure 2b , which can also be used with both output types, is an opt ional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if us ing a non-standard termination, it is recommended to contact idt and c onfirm if the outpu t structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o z t z o z t z t 2 z t 2 figure 2a. standard termination figure 2b. optional termination
ICS844011ag revision a august 27, 2012 10 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator schematic layout figure 3 shows an example of ICS844011 application schematic in which the device is operated at v dd = 3.3v. the schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. for example oe can be configured from an fpga instead of set with pull up and pull down resistors as shown. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the v dd pin from power supply is required. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as poss ible. if space is limited, the 0.1uf capacitor on the vdd pin must be placed on the device side with direct return to the ground plane though vias. the remaining filter components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequencies. this low-pass filter starts to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is re commended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. figure 3. ICS844011 application schematic 3.3v c5 0.1uf c4 10uf vdd fb1 blm18bb221sn1 1 2 place 0.1uf bypass caps directly adjacent to the respective vdd and vdda pins. c3 0.1uf oe ru 2 not i nst all vcc ru1 1k vcc rd 2 1k rd1 not install set logic input to '1' to logic input pins logic control input examples set logic input to '0' to logic input pins vdda r1 10 c6 10uf c7 0. 1 u f vdda vdd c2 33pf c1 27pf x1 25mhz (18pf ) u1 vdda 1 nq 6 xtal _ o ut 3 xtal _ i n 4 vd d 8 q 7 gnd 2 oe 5 lvds receiv er + - zo = 50 ohm zo = 50 ohm r2 100
ICS844011ag revision a august 27, 2012 11 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator power considerations this section provides information on power dissipation and junction temperature for the ICS844011. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS844011 is the sum of the core power plus the analog power plus the power dissipated in t he load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (108ma + 12ma) = 415.8mw 2. junction temperature. junction temperature, tj, is the temper ature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 129.5c/w per table 7 below. therefore, tj for an ambient temperatur e of 70c with all outputs switching is: 70c + 0.416w * 129.5c/w = 123.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 8 lead tssop, forced convection ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 129.5c/w 125.5c/w 123.5c/w
ICS844011ag revision a august 27, 2012 12 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator reliability information table 8. ja vs. air flow table for a 8-lead tssop transistor count the transistor count for ICS844011 is: 2533 package outline and package dimensions package outline - g suffix for 8 lead tssop table 9. package dimensions reference document: jede c publication 95, mo-153 ja vs. air flow meters per second 012 . 5 multi-layer pcb, jedec standard test boards 129.5c/w 125.5c/w 123.5c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS844011ag revision a august 27, 2012 13 ?2012 integrated device technology, inc. ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator ordering information table 10. ordering information part/order number marking package shipping packaging temperature 844011aglf 011al lead-free, 8-lead tssop tube 0 c to 70 c 844011aglft 011al lead-free, 8-lead tssop tape & reel 0 c to 70 c
ICS844011 data sheet femtoclock ? crystal-to-lvds clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt s sole discretion. all information in this document, including descriptions of product features and performance, is subj ect to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idts products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property righ ts of idt or any third parties. idts products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to sig- nificantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 weve got your timing solution

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